AR8327-AL1A-R datasheet(61/394 Pages) ETC2

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Atheros Communications, Inc.

AR8327/AR8327N Seven-port Gigabit Ethernet

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Table 3-6 summarizes the PORT5 PAD MODE CTRL Register.

3.2.4

PORT6 PAD MODE CTRL

Address: 0x000C

HW RST

Table 3-6.

PORT5 PAD MODE CTRL Register

Bit

R/W

Inital

Value

Mnemonic

Description

31:27

R/O

Reserved

R/W

Mac5_rgmii_en

1'b1 Mac5 connected to cpu through

RGMII interface

R/W

Mac5_rgmii_txclk_delay_en

1'b1 RGMII interface txclk(input from

cpu) will be delay, delay value depend

on bit23:bit22

R/W

Mac5_rgmii_rxclk_delay_en

1'b1 RGMII interface rxclk will be

delay,

1000M: delay 2ns output to cpu

10/100M: delay value depend on

bit21:bit20

23:22

R/W

Mac5_rgmii_txclk_delay_sel

2'b11 ~ 2'b00

Control the delay value of RGMII

interface txclk,2'b11 has the max delay

21:20

R/W

Mac5_rgmii_rxclk_delay_sel

2'b11 ~ 2'b00

Control the delay value of RGMII

interface rxclk,2'b11 has the max delay

19:12

R/O

Reserved

R/W

Mac5_phy_mii_pipe_rxclk_sel

1'b1 select clock edge for rxpipe,default

is invert

R/W

Mac5_phy_mii_en

1'b1: mac5 connected to cpu through

MII interface, phy mode

R/W

Mac5_phy_mii_txclk_sel

1'b1 select invert clock output for port5

phymode ,MII interface txclk

R/W

Mac5_phy_mii_rxclk_sel

1'b1 select invert clock output for port5

phymode ,MII interface rxclk

7;3

R/W

Reserved

R/W

Mac5_mac_mii_en

1'b1 Mac5 connected to cpu through

MII interface, mac mode

R/W

Mac5_mac_mii_txclk_sel

1'b1 select invert clock input for port5

macmode, MII interface txclk

R/W

Mac5_mac_mii_rxclk_sel

1'b1 select invert clock input for port5

macmode, MII interface rxclk

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