AR8327-AL1A-R datasheet(70/394 Pages) ETC2

70 / 394 page

70 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch

Atheros Communications, Inc.

70 • June 2011

COMPANY CONFIDENTIAL

3.2.13

MDIO Master Control

Address 0x003C

SFT&HW RST

Table 3-16 summarizes the MDIO Master Control Register

3.2.14

BIST_CTRL

Address 0x0040

SFT&HW RST

R/W

SGMII_CLK125M_RX_SEL

SGMII interface Rx clock selection

1 = inverse clock

R/W

SGMII_CLK125M_TX_SEL

SGMII interface Tx clock selection

1 = inverse clock

17:10

R/W

RESERVED

9:0

R/W

RESERVED

Table 3-15.

MInterface High Address Register

Bit

R/W

Inital

Value

Mnemonic

Description

Table 3-16.

MDIO Master Control Register

Bit

R/W

Inital

Value

Mnemonic

Description

R/W

MDIO_BUSY

1'b1: internal MDIO interface is busy.

This bit should be set to 1'b1 when cpu read or

write phy register through internal mdio

interface, and should be clear after hardware

finish the command.

R/O

MDIO_MASTER_EN

1''b1: use mdio master to config phy register. Mdc

should be changed to internal mdc to phy.

29:28

R/W

Reserved

R/O

MDIO_CMD

1'b0: write

1'b1: read

R/W

MDIO_SUP_PRE

1'b1: suppress preamble enable

1'b0: with 32 bits preamble

25:21

R/O

PHY_ADDR

Phy address

20:16

R/W

REG_ADDR

Phy register address

15:0

R/W

MDIO_DATA

When write, these bits are data written to phy

from phy register.

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