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AR8327-AL1A-R 데이터시트(PDF) 388 Page - List of Unclassifed Manufacturers |
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AR8327-AL1A-R 데이터시트(HTML) 388 Page - List of Unclassifed Manufacturers |
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388 / 394 page ![]() 388 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch Atheros Communications, Inc. 388 • June 2011 COMPANY CONFIDENTIAL 4.5.4 RGMII Timing Figure 4-5 shows the RGMII timing diagram. Table 4-8. Reduced GMII Timing Figure 4-5. RGMII Timing Diagram GTXCLK TXCTL TXD[3:0] TskewR RXCLK RXCTL RXD[3:0] TskewT at Transmitter(PHY mode) at Receiver(PHY mode) Symbol Parameter Min Typ Max Unit TskewT Data to Clock output skew -0.5 0.5 ns TskewR Data to Clock input skew 1 2.6 ns Data Input to Clock Edge 1 ns Hold Time 1 ns |
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