VR4102 datasheet(173/701 Pages) NEC

173 / 701 page

CHAPTER 6 EXCEPTION PROCESSING

173

6.4 DETAILS OF EXCEPTIONS

This section describes causes, processes, and services of the VR4102’s exceptions.

6.4.1 Exception Types

This section gives sample exception handler operations for the following exception types:

— Cold Reset

— Soft Reset

— NMI

— Cache error

— Remaining processor exceptions

When the EXL and ERL bits in the Status register are 0, either User, Supervisor, or Kernel operating mode is

specified by the KSU bits in the Status register. When either the EXL or ERL bit is set to 1, the processor is in

Kernel mode.

When the processor takes an exception, the EXL bit is set to 1, meaning the system is in Kernel mode. After

saving the appropriate state, the exception handler typically resets the EXL bit back to 0. The exception handler

sets the EXL bit to 1 so that the saved state is not lost upon the occurrence of another exception while the saved

state is being restored.

Returning from an exception also resets the EXL bit to 0. For details, see Chapter 27.

6.4.2 Exception Vector Locations

The Cold Reset, Soft Reset, and NMI exceptions are always branched to the following reset exception vector

address (virtual). This address is in an uncached, unmapped space.

— 0xBFC0 0000 in 32-bit mode

— 0xFFFF FFFF BFC0 0000 in 64-bit mode

Addresses for the remaining exceptions are a combination of a vector offset and a base address.

64-/32-bit mode exception vectors and their offsets are shown below.

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