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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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VR4102 데이터시트(PDF) 101 Page - NEC |
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VR4102 데이터시트(HTML) 101 Page - NEC |
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101 / 701 page  CHAPTER 4 VR4102 PIPELINE 101 Table 4-1. Description of Pipeline Activities during Each Stage Cycle Phase Mnemonic Description IDC Instruction cache address decode )1 ITLB Instruction address translation ICA Instruction cache array access IF )2 ITC Instruction tag check )1 IDEC Instruction decode RF Register operand fetch RF )2 BAC Branch address calculation EX Execution stage DVA Data virtual address calculation )1 SA Store align DCA Data cache address decode/array access EX )2 DTLB Data address translation DLA Data cache load align DTC Data tag check DC )1 DTD Data transfer to data cache DCW Data cache write WB )1 WB Write back to register file |
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