VR4102 datasheet(155/701 Pages) NEC

155 / 701 page

CHAPTER 5 MEMORY MANAGEMENT SYSTEM

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5.5.10 TLB Misses

If there is no TLB entry that matches the virtual address, a TLB Refill (miss) exception occurs

Note. If the access

control bits (D and V) indicate that the access is not valid, a TLB Modified or TLB Invalid exception occurs. If the C

bit is 010, the retrieved physical address directly accesses main memory, bypassing the cache.

Note

See Chapter 6 for details of the TLB Miss exception.

5.5.11 TLB Instructions

The instructions used for TLB control are described below.

(1) Translation lookaside buffer probe (TLBP)

The translation lookaside buffer probe (TLBP) instruction loads the Index register with a TLB number that

matches the content of the EntryHi register. If there is no TLB number that matches the TLB entry, the highest-

order bit of the Index register is set.

(2) Translation lookaside buffer read (TLBR)

The translation lookaside buffer read (TLBR) instruction loads the EntryHi, EntryLo0, EntryLo1, and PageMask

registers with the content of the TLB entry indicated by the content of the Index register.

(3) Translation lookaside buffer write index (TLBWI)

The translation lookaside buffer write index (TLBWI) instruction writes the contents of the EntryHi, EntryLo0,

EntryLo1, and PageMask registers to the TLB entry indicated by the content of the Index register.

(4) Translation lookaside buffer write random (TLBWR)

The translation lookaside buffer write random (TLBWR) instruction writes the contents of the EntryHi, EntryLo0,

EntryLo1, and PageMask registers to the TLB entry indicated by the content of the Random register.

VR4102 데이터시트(PDF) 155 Page - NEC