MPC821 datasheet(199/242 Pages) NXP

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MPC860TFADS Daughter Board Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

PM1 Interconnect Signals’ Differences" on page 49

TABLE 5-9. PM1 Interconnect Signals

Pin No.

Signal Name

Attribute

Description

BB~

I/O, L

MPC’s Bus Busy signal. Pulled - up on the FADS.

VCC

DRM_W~

I,L

MPC’s GPL0~ lines used as R/W~ signal for the DRAM simm or

as A10 line for the SDRAM.

VCC

5V Bus.

TEA~

I/O, L,

O.D.

Transfer Error Acknowledge. Pulled-up, not driven on board.

VCC

BR~

I/O,L

MPC’s Bus Request signal. Pulled - up on the FADS, but

otherwise unused.

VCC

BURST~

I/O, L

MPC’s Burst indication. Pulled - up on the FADS, but otherwise

unused.

VCC

GPL4A~

X,L

UPMA general purpose line 4. Not used on the FADS.

VCC

TA~

I/O, L

MPC’s transfer Acknowledge signal. Indicates end of bus cycle,

used with FADS logic.

VCC

TS~

I/O, L

MPC’s Transfer Start indication. Pulled - up, but otherwise

unused on the FADS.

VCC

GPL5B~

O, L

General Purpose Line 5 of UPMB. Not used on the FADS.

VCC

BG~

I/O, L

MPC’s Bus grant signal. Pulled - up on the FADS, but otherwise

unused.

VCC

GPL4B~

O, L

General Purpose Line 4 of UPMB. Not used on the FADS.

VCC

R_W~

I/O, L

MPC’s Read/Write~ indication. Pulled - up on the FADS and used

by FADS logic.

VCC

BCSRCS~

I/O, L

In fact CS1~ of the MPC. Used as chip-select for the BCSRs.

Pulled - up. When BCSR is removed from the local map, may be

used off-board via the daughter-board’s expansion connectors.

VCC

5V Bus.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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