MPC821 datasheet(200/242 Pages) NXP

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Support Information

MPC860TFADS Daughter Board Design Specification—Rev 0.1

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

GPL5A~

X,L

UPMA general purpose line 5. Not used on the FADS.

VCC

5V Bus.

BI~

I/O,L

MPC’s Burst Inhibit input. Pulled - up, but otherwise unused on

the FADS.

N.C.

Not Connected. Reserved.

CS7~

GND

FADS Ground plane.

CS5~

MPC’s Chip Select line 5. Unused on the FADS.

GND

CE1A~

I, L

PC-Card Enable 1 for PCMCIA slot A. Enables the EVEN address

bytes. Used by on-board PCMCIA port.

GND

F_CS~

I/O, L

In fact MPC’s chip-select line 0. Used as chip-select for the Flash

Simm. Pulled - up. When the Flash is disabled via BCSR, may be

used off-board via the daughter-board’s expansion connectors.

GND

CS6~

MPC’s Chip Select line 6. Unused on the FADS.

GND

CE2A~

I, L

PC-Card Enable 2 for PCMCIA slot A. Enables the ODD address

bytes. Used by on-board PCMCIA port.

GND

DRMCS2~

I/O, L

In fact MPC’s chip-select line 3. Used as chip-select line for the

2’nd bank of the Dram Simm. Pulled - up. When the Dram is

disabled via BCSR or when a single-bank Dram Simm is being

used - may be used off-board via the daughter board’s expansion

connectors.

GND

DRMCS1~

I/O, L

In fact MPC’s chip-select line 2. Used as chip-select line for the

1’st bank of the Dram Simm. Pulled - up. When the Dram is

disabled via BCSR - may be used off-board via the daughter

board’s expansion connectors.

GND

SDRMCS~

I/O, L

In fact MPC’s chip-select line 4. Used as chip-select for the

Synchronous Dram. Pulled - up. When the SDRAM is disabled via

BCSR, may be used off-board via the daughter board

GND

GPL3~

I/O, L

UPMA or UPMB general purpose line 3. Used as WR~ signal for

the SDRAM.

GND

TABLE 5-9. PM1 Interconnect Signals

Pin No.

Signal Name

Attribute

Description

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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