MPC821 datasheet(205/242 Pages) NXP

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MOTOROLA

MPC860TFADS Daughter Board Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

VF2

I/O

IP_B3/IWP2/VF2. PCMCIA slot B Input Port 3 or Instruction

Watch-Point 2 or Visible Instruction Queue Flushes Status 2. For

MPC823 or MPC850 daughter boards - conﬁgured as IP_B3. For

all other daughter boards, conﬁgured as VF2, but may be

conﬁgured to alternate function as no use is done with VF2 on the

FADS.

GND

VF0

I/O

IP_B4/LWP0/VF0. PCMCIA slot B Input Port 4 or Data Watch-

Point 0 or Visible Instruction Queue Flushes Status 0. For

MPC823 or MPC850 daughter boards - conﬁgured as IP_B4. For

all other daughter boards, conﬁgured as VF0, but may be

conﬁgured to alternate function as no use is done with VF0 on the

FADS.

GND

IRQ3~

I/O, L

IRQ3~/CR~. MPC’s interrupt request 3 or Cancel Reservation.

Pulled - up but otherwise not used on the FADS.

GND

FRZ

I, X

Freeze / IRQ6~. MPC debug state indication or Interrupt request

line 6. Used by the debug port controller as debug state

indication. May be conﬁgured to alternate function provided that

VFLS(0:1) function as VFLS and J1 is moved to position 1-2.

GND

IRQ2~

I/O, L

RSV~/IRQ2~. Reservation or Interrupt Request 2. Pulled - up but

otherwise unused on the FADS.

GND

AT3

I/O

IP_B7/PTR/AT3. PCMCIA slot B Input Port 7 or Program Trace

(instruction fetch indication or Address Type 3. For MPC823 or

MPC850 daughter boards - conﬁgured as IP_B7. For all other

daughter boards, conﬁgured as AT3, but may be conﬁgured to

alternate function as no use is done with AT3 on the FADS.

GND

SPARE4

I/O

MPC’s spare line 4. Pulled - up but otherwise unused on the

FADS.

GND

TABLE 5-10. PM2 Interconnect Signals

Pin No.

Signal Name

Attribute

Description

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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