HCS08 datasheet(63/290 Pages) MOTOROLA

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Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

MC9S08GB/GT

Section 5 Resets, Interrupts, and System Configuration

5.1 Introduction

This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts

in the MC9S08GB/GT. Some interrupt sources from peripheral modules are discussed in greater detail

within other sections of this data manual. This section gathers basic information about all reset and

interrupt sources in one place for easy reference. A few reset and interrupt sources, including the computer

operating properly (COP) watchdog and real-time interrupt (RTI), are not part of on-chip peripheral

systems with their own sections but are part of the system control logic.

5.2 Features

Reset and interrupt features include:

•

Multiple sources of reset for flexible system configuration and reliable operation:

–

Power-on detection (POR)

–

Low voltage detection (LVD) with enable

–

External RESET pin with enable

–

COP watchdog with enable and two timeout choices

–

Illegal opcode

–

Serial command from a background debug host

•

Reset status register (SRS) to indicate source of most recent reset

•

Separate interrupt vectors for each module (reduces polling overhead) (see Table 5-1)

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