HCS08 datasheet(91/290 Pages) MOTOROLA

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Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

MC9S08GB/GT

6.3.5 FLL Engaged, External Clock (FEE) Mode

The FLL engaged external (FEE) mode is entered when any of the following conditions occur:

•

CLKS = 11 and ERCS and DCOS are both high.

•

The DCO stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 11.

In FEE mode, the reference clock is derived from the external reference clock ICGERCLK, and the FLL

loop will attempt to lock the ICGDCLK frequency to the desired value, as selected by the MFD bits. To

run in FEE mode, there must be a working 32 kHz–100 kHz or 2 MHz–10 MHz external clock source. The

maximum external clock frequency is limited to 10 MHz in FEE mode to prevent over-clocking the DCO.

The minimum multiplier for the FLL, from Table 6-8 is 4. Since 4 X 10 MHz is 40MHz, which is the

operational limit of the DCO, the reference clock cannot be any faster than 10 MHz.

6.3.5.1 FLL Engaged External Unlocked

FEE unlocked is entered when FEE is entered and the count error (

∆n) output from the subtractor is greater

than the maximum nunlock or less than the minimum nunlock, as required by the lock detector to detect the

unlock condition.

The ICG will remain in this state while the count error (

∆n) is greater than the maximum n

lock or less than

the minimum nlock, as required by the lock detector to detect the lock condition.

In this state, the pulse counter, subtractor, digital loop filter, and DCO form a closed loop and attempt to

lock it according to their operational descriptions later in this section. Upon entering this state and until

the FLL becomes locked, the output clock signal ICGOUT frequency is given by fICGDCLK / (2×R) This

extra divide by two prevents frequency overshoots during the initial locking process from exceeding

chip-level maximum frequency specifications. Once the FLL has locked, if an unexpected loss of lock

causes it to re-enter the unlocked state while the ICG remains in FEE mode, the output clock signal

ICGOUT frequency is given by fICGDCLK / R.

6.3.5.2 FLL Engaged External Locked

FEE locked is entered from FEE unlocked when the count error (

∆n) is less than n

lock (max) and greater

than nlock (min) for a given number of samples, as required by the lock detector to detect the lock

condition. The output clock signal ICGOUT frequency is given by fICGDCLK/R. In FLL engaged external

locked, the filter value is only updated once every four comparison cycles. The update made is an average

of the error measurements taken in the four previous comparisons.

6.3.6 FLL Lock and Loss-of-Lock Detection

To determine the FLL locked and loss-of-lock conditions, the pulse counter counts the pulses of the DCO

for one comparison cycle (see Table 6-3 for explanation of a comparison cycle) and passes this number

to the subtractor. The subtractor compares this value to the value in MFD and produces a count error,

∆n.

To achieve locked status,

∆n must be between n

lock (min) and nlock (max). Once the FLL has locked, ∆n

must stay between nunlock (min) and nunlock (max) to remain locked. If ∆n goes outside this range

unexpectedly, the LOLS status bit is set and remains set until acknowledged or until the MCU is reset.

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