HCS08 datasheet(20/290 Pages) MOTOROLA

20 / 290 page

Introduction

MC9S08GB/GT

MOTOROLA

Figure 1-2 MC9S08GTxx Block Diagram

PTD3/TPM2CH0

PTD4/TPM2CH1

PTC1/RxD2

PTC0/TxD2

VSS

VDD

PTE3/MISO

PTE2/SS

PTA7/KBIP7–

PTE0/TxD1

PTE1/RxD1

PTD1/TPM1CH1

PTD0/TPM1CH0

PTC6 (NOTE 6)

PTC5 (NOTE 6)

PTC4

PTC3/SCL

PTC2/SDA

8-BIT KEYBOARD

INTERRUPT MODULE (KBI)

IIC MODULE (IIC)

SERIAL PERIPHERAL

INTERFACE MODULE (SPI)

USER FLASH

USER RAM

(GT60 = 4096 BYTES)

DEBUG

MODULE (DBG)

(GT60 = 61,268 BYTES)

HCS08 CORE

NOTES:

1. Port pins are software configurable with pullup device if input port.

2. Pin contains software configurable pullup/pulldown device if IRQ enabled (IRQPE = 1).

3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD.

4. Pin contains integrated pullup device.

5. High current drive

6. PTC[6:5] are not available on the 42-pin SDIP package.

7. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1).

8. Only two timer channels per TPM are bonded out. All channels are available for use.

NOTE 1

3-CHANNEL TIMER/PWM

MODULE (TPM1)

PTB7/AD7–

PTE5/SPSCK

PTE4/MOSI

INTERFACE MODULE (SCI2)

HCS08 SYSTEM CONTROL

RESETS AND INTERRUPTS

MODES OF OPERATION

POWER MANAGEMENT

VOLTAGE

REGULATOR

RTI

SERIAL COMMUNICATIONS

COP

IRQ

LVD

INTERNAL BUS

LOW-POWER OSCILLATOR

INTERNAL CLOCK

GENERATOR (ICG)

RESET

VSSAD

VDDAD

VREFH

VREFL

ANALOG-TO-DIGITAL

CONVERTER (ATD)

INTERFACE MODULE (SCI1)

SERIAL COMMUNICATIONS

5-CHANNEL TIMER/PWM

MODULE (TPM2)

NOTE 1

PTA0/KBIP0

PTB0/AD0

PTG2/EXTAL

PTG0/BKGD/MS

PTG1/XTAL

NOTE 4

NOTES 1, 5

(GT32 = 32,768 BYTES)

(GT32 = 2048 BYTES)

IRQ

NOTES 2, 3

10-BIT

NOTES 1, 7

NOTE 1

(NOTE 8)

CPU

BDC

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