HCS08 datasheet(78/290 Pages) MOTOROLA

78 / 290 page

Resets, Interrupts, and System Configuration

MC9S08GB/GT

MOTOROLA

5.8.8 System Power Management Status and Control 2 Register (SPMSC2)

This register is used to report the status of the low voltage warning function, and to configure the stop

mode behavior of the MCU.

Figure 5-9 System Power Management Status and Control 2 Register (SPMSC2)

LVWF — Low-Voltage Warning Flag

The LVWF bit indicates the low voltage warning status.

1 = Low voltage warning is present or was present.

0 = Low voltage warning not present.

LVWACK — Low-Voltage Warning Acknowledge

The LVWF bit indicates the low voltage warning status.

Writing a logic 1 to LVWACK clears LVWF to a logic 0 if a low voltage warning is not present.

LVDV — Low-Voltage Detect Voltage Select

The LVDV bit selects the LVD trip point voltage (VLVD).

1 = High trip point selected (VLVD = VLVDH).

0 = Low trip point selected (VLVD = VLVDL).

LVWV — Low-Voltage Warning Voltage Select

The LVWV bit selects the LVW trip point voltage (VLVW).

1 = High trip point selected (VLVW = VLVWH).

0 = Low trip point selected (VLVW = VLVWL).

PPDF — Partial Power Down Flag

The PPDF bit indicates that the MCU has exited the stop2 mode.

1 = Stop2 mode recovery.

0 = Not stop2 mode recovery.

Bit 7

54321

Bit 0

Read:

LVWF

LVDV

LVWV

PPDF

PDC

PPDC

Write:

LVWACK

PPDACK

Power-on reset:

0(1)

NOTES:

1. LVWF will be set in the case when VSupply transitions below the trip point or after reset and VSupply is already

below VLVW.

0000

LVD reset:

0(1)

0000

Any other reset:

0(1)

0000

= Unimplemented or Reserved

U = Unaffected by reset

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