HCS08 datasheet(93/290 Pages) MOTOROLA

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Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

MC9S08GB/GT

6.3.8 Clock Mode Requirements

A clock mode is requested by writing to CLKS1:CLKS0 and the actual clock mode is indicated by

CLKST1:CLKST0. Provided minimum conditions are met, the status shown in CLKST1:CLKST0 should

be the same as the requested mode in CLKS1:CLKS0. Table 6-3 shows the relationship between CLKS,

CLKST, and ICGOUT. It also shows the conditions for CLKS = CLKST or the reason CLKS

≠ CLKST.

NOTE:

If a crystal will be used before the next reset, then be sure to set REFS = 1 and

CLKS = 1x on the first write to the ICGC1 register. Failure to do so will result in

“locking” REFS = 0 which will prevent the oscillator amplifier from being enabled

until the next reset occurs.

Table 6-3 ICG State Table

Actual

Mode

(CLKST)

Desired

Mode

(CLKS)

Range

Reference

Frequency

(fREFERENCE)

Comparison

Cycle Time

ICGOUT

Conditions(1)

for

CLKS = CLKST

NOTES:

1. CLKST will not update immediately after a write to CLKS. Several bus cycles are required before CLKST updates to the

new value.

Reason

CLKS1 =

CLKST

Off

(XX)

Off

(XX)

—

FBE

(10)

—

ERCS = 0

SCM

(00)

SCM

(00)

fICGIRCLK/7

(2)

2. The reference frequency has no effect on ICGOUT in SCM, but the reference frequency is still used in making the

comparisons that determine the DCOS bit

8/fICGIRCLK

ICGDCLK/R

Not switching from

FBE to SCM

—

FEI

(01)

fICGIRCLK/7

(1)

8/fICGIRCLK

ICGDCLK/R

—

DCOS = 0

FBE

(10)

fICGIRCLK/7

(1)

8/fICGIRCLK

ICGDCLK/R

—

ERCS = 0

FEE

(11)

fICGIRCLK/7

(1)

8/fICGIRCLK

ICGDCLK/R

—

DCOS = 0 or

ERCS = 0

FEI

(01)

FEI

(01)

fICGIRCLK/7

8/fICGIRCLK

ICGDCLK/R

DCOS = 1

—

FEE

(11)

fICGIRCLK/7

8/fICGIRCLK

ICGDCLK/R

—

ERCS = 0

FBE

(10)

FBE

(10)

—

ICGERCLK/R

ERCS = 1

—

FEE

(11)

—

ICGERCLK/R

—

LOCS = 1 &

ERCS = 1

FEE

(11)

FEE

(11)

fICGERCLK

2/fICGERCLK

ICGDCLK/R(3)

3. After initial LOCK; will be ICGDCLK/2R during initial locking process and while FLL is re-locking after the MFD bits are

changed.

ERCS = 1 and

DCOS = 1

—

fICGERCLK

128/fICGERCLK

ICGDCLK/R(2)

ERCS = 1 and

DCOS = 1

—

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