HCS08 datasheet(67/290 Pages) MOTOROLA

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Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

MC9S08GB/GT

5.5.2.1 Pin Configuration Options

The IRQ pin enable (IRQPE) control bit in the IRQSC register must be 1 in order for the IRQ pin to act as

the interrupt request (IRQ) input. As an IRQ input, the user can choose the polarity of edges or levels

detected (IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD), and whether an

event causes an interrupt or just sets the IRQF flag which can be polled by software.

When the IRQ pin is configured to detect rising edges, an optional pulldown resistor is available rather

than a pullup resistor. BIH and BIL instructions may be used to detect the level on the IRQ pin when the

pin is configured to act as the IRQ input.

NOTE:

The voltage measured on the pulled up IRQ pin may be as low as VDD – 0.7 V. The

internal gates connected to this pin are pulled all the way to VDD. All other pins

with enabled pullup resistors will have an unloaded measurement of VDD.

5.5.2.2 Edge and Level Sensitivity

The IRQMOD control bit reconfigures the detection logic so it detects edge events and pin levels. In this

edge detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQ pin

changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be cleared)

as long as the IRQ pin remains at the asserted level.

5.5.3 Interrupt Vectors, Sources, and Local Masks

Table 5-1 provides a summary of all interrupt sources. Higher-priority sources are located toward the

bottom of the table. The high-order byte of the address for the interrupt service routine is located at the

first address in the vector address column, and the low-order byte of the address for the interrupt service

routine is located at the next higher address.

When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt

enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in

the CCR) is 0, the CPU will finish the current instruction, stack the PCL, PCH, X, A, and CCR CPU

registers, set the I bit, and then fetch the interrupt vector for the highest priority pending interrupt.

Processing then continues in the interrupt service routine.

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