HCS08 datasheet(165/290 Pages) MOTOROLA

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Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

165

MC9S08GB/GT

10.7.1 Timer x Status and Control Register (TPMxSC)

TPMxSC contains the overflow status flag and control bits which are used to configure the interrupt

enable, TPM configuration, clock source, and prescale divisor. These controls relate to all channels within

this timer module.

Figure 10-5 Timer x Status and Control Register (TPMxSC)

TOF — Timer Overflow Flag

This flag is set when the TPM counter changes to $0000 after reaching the modulo value programmed

in the TPM counter modulo registers. When the TPM is configured for CPWM, TOF is set after the

counter has reached the value in the modulo register, at the transition to the next lower count value.

Clear TOF by reading the TPM status and control register when TOF is set and then writing a logic 0

to TOF. If another TPM overflow occurs before the clearing sequence is complete, the sequence is

reset so TOF would remain set after the clear sequence was completed for the earlier TOF. Reset clears

the TOF bit. Writing a logic 1 to TOF has no effect.

1 = TPM counter has overflowed.

0 = TPM counter has not reached modulo value or overflow.

TOIE — Timer Overflow Interrupt Enable

This read/write bit enables TPM overflow interrupts. If TOIE is set, an interrupt is generated when

TOF equals 1. Reset clears TOIE.

1 = TOF interrupts enabled.

0 = TOF interrupts inhibited (use software polling).

CPWMS — Center-Aligned PWM Select

This read/write bit selects CPWM operating mode. Reset clears this bit so the TPM operates in

up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting

CPWMS reconfigures the TPM to operate in up/down-counting mode for CPWM functions. Reset

clears the CPWMS bit.

1 = All TPMx channels operate in center-aligned PWM mode.

0 = All TPMx channels operate as input capture, output compare, or edge-aligned PWM mode as

selected by the MSnB:MSnA control bits in each channel’s status and control register.

Bit 7

654321

Bit 0

Read:

TOF

TOIE

CPWMS

CLKSB

CLKSA

PS2

PS1

PS0

Write:

Reset:

00000000

= Unimplemented or Reserved

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