HCS08 datasheet(170/290 Pages) MOTOROLA

170 / 290 page

Timer/PWM (TPM) Module

MC9S08GB/GT

170

MOTOROLA

Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated

to any timer channel functions. This function is typically used to temporarily disable an input capture

channel or to make the timer pin available as a general-purpose I/O pin when the associated timer

channel is set up as a software timer that does not require the use of a pin. This is also the setting

required for channel 0 when the TPMxCH0 pin is used as an external clock input.

10.7.5 Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL)

These read/write registers contain the captured TPM counter value of the input capture function or the

output compare value for the output compare or PWM functions. The channel value registers are cleared

by reset.

Figure 10-11 Timer x Channel Value Register High (TPMxCnVH)

Figure 10-12 Timer x Channel Value Register Low (TPMxCnVL)

In input capture mode, reading either byte (TPMxCnVH or TPMxCnVL) latches the contents of both bytes

into a buffer where they remain latched until the other byte is read. This latching mechanism also resets

(becomes unlatched) when the TPMxCnSC register is written.

In output compare or PWM modes, writing to either byte (TPMxCnVH or TPMxCnVL) latches the value

into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the

timer channel value registers. This latching mechanism may be manually reset by writing to the

TPMxCnSC register.

This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various

compiler implementations.

Bit 7

654321

Bit 0

Read:

Bit 15

Bit 8

Write:

Reset:

00000000

Bit 7

654321

Bit 0

Read:

Bit 7

654321

Bit 0

Write:

Reset:

00000000

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