EM351-RTR datasheet(126/240 Pages) ETC2

126 / 240 page

EM351 / EM357

Figure 9-5. Counter Timing Diagram, Update Event when TIM_ARBE = 0 (TIMx_ARR not buffered)

Figure 9-6. Counter Timing Diagram, Update Event when TIM_ARBE = 1 (TIMx_ARR buffered)

9.3.2.2

Down-Counting Mode

In down-counting mode, the counter counts from the auto-reload value (contents of the TIMx_ARR register)

down to 0, then restarts from the auto-reload value and generates a counter underflow event.

A UEV can be generated at each counter underflow, by setting the TIM_UG bit in the TIMx_EGR register, or by

using the slave mode controller. Software can disable the UEV by setting the TIM_UDIS bit in the TIMx_CR1

occurs until the TIM_UDIS bit is written to 0. However, the counter restarts from the current auto-reload

value, whereas the prescaler’s counter restarts from 0, but the prescale rate doesn’t change.

In addition, if the TIM_URS bit in the TIMx_CR1 register is set, setting the TIM_UG bit generates a UEV, but

without setting the INT_TIMUIF flag. Thus no interrupt request is sent. This avoids generating both update and

capture interrupts when clearing the counter on the capture event.

When a UEV occurs, the update flag (the INT_TIMUIF bit in the INT_TIMxFLAG register) is set (unless TIM_USR

is 1) and the following registers are updated:

9-6

120-035X-000D

Preliminary

EM351-RTR 데이터시트(PDF) 126 Page - List of Unclassifed Manufacturers