EM351-RTR datasheet(127/240 Pages) ETC2

127 / 240 page

EM351 / EM357

The prescaler shadow register is reloaded with the buffer value (contents of the TIMx_PSC register).

The auto-reload active register is updated with the buffer value (contents of the TIMx_ARR register). The

auto-reload is updated before the counter is reloaded, so that the next period is the expected one.

Figure 9-7 and Figure 9-8 show some examples of the counter behavior for different clock frequencies when

TIMx_ARR = 0x36.

Figure 9-7. Counter Timing Diagram, Internal Clock Divided by 1

Figure 9-8. Counter Timing Diagram, Internal Clock Divided by 4

9.3.2.3

Center-Aligned Mode (Up/Down Counting)

In center-aligned mode, the counter counts from 0 to the auto-reload value (contents of the TIMx_ARR

generates a counter underflow event. Then it restarts counting from 0.

In this mode, the direction bit (TIM_DIR in the TIMx_CR1 register) cannot be written. It is updated by hardware

and gives the current direction of the counter.

The UEV can be generated at each counter overflow and at each counter underflow. Setting the TIM_UG bit in

the TIMx_EGR register by software or by using the slave mode controller also generates a UEV. In this case,

the both the counter and the prescaler’s counter restart counting from 0.

Software can disable the UEV by setting the TIM_UDIS bit in the TIMx_CR1 register. This avoids updating the

shadow registers while writing new values in the buffer registers. Then no UEV occurs until the TIM_UDIS bit

has been written to 0. However, the counter continues counting up and down, based on the current auto-

reload value.

In addition, if the TIM_URS bit in the TIMx_CR1 register is set, setting the TIM_UG bit generates a UEV, but

without setting the INT_TIMUIF flag. Thus no interrupt request is sent. This avoids generating both update and

capture interrupt when clearing the counter on the capture event.

9-7

120-035X-000D

Preliminary

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