MPC8569E datasheet(56/127 Pages) FREESCALE

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MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Ethernet Interface

Freescale Semiconductor

2.6.3.1.2

GMII Receive AC Timing Specifications

The following table provides the GMII receive AC timing specifications.

The following figure provides the GMII AC test load.

Figure 13. GMII AC Test Load

The following figure shows the GMII receive AC timing diagram.

Figure 14. GMII Receive AC Timing Diagram

2.6.3.2

MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

Table 26. GMII Receive AC Timing Specifications

For recommended operating conditions, see Table 3

Parameter

Symbol

Min

Typ

Max

Unit

Note

RX_CLK clock period

tGRX

7.5

—

RX_CLK duty cycle

tGRXH/tGRX

—

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK

tGRDVKH

2.0

—

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK

tGRDXKH

0.2

—

RX_CLK clock rise time (20%–80%)

tGRXR

——

1.0

RX_CLK clock fall time (80%–20%)

tGRXF

——

1.0

Note:

1. The frequency of RX_CLK should not exceed frequency of gigabit Ethernet reference clock by more than 300 ppm

2. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is

guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing

Output

Z0 = 50 Ω

LVDD/2

RL = 50 Ω

RX_CLK

RXD[7:0]

tGRDXKH

tGRX

tGRXH

tGRXR

tGRXF

tGRDVKH

RX_DV

RX_ER

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