MPC8569E datasheet(85/127 Pages) FREESCALE

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PCI Express

MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

2.9.2.5

SerDes Transmitter and Receiver Reference Circuits

The following figure shows the reference circuits for SerDes data lane’s transmitter and receiver.

Figure 45. SerDes Transmitter and Receiver Reference Circuits

The DC and AC specification of SerDes data lanes are defined in each interface protocol section (SGMII, PCI Express, or Serial

Rapid IO) in this document based on the application usage

•

Section 2.6.4, “SGMII Interface Electrical Characteristics”

•

Section 2.10, “PCI Express”

•

Section 2.11, “Serial RapidIO (SRIO)”

Note that external AC-coupling capacitor is required for the above three serial transmission protocols with the capacitor value

defined in the specification of each protocol section.

2.9.2.6

Clocking Dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all

times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.

2.10

PCI Express

This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8569E.

2.10.1

PCI Express DC Requirements for SD_REF_CLK and SD_REF_CLK

For more information, see Section 2.9.2.3, “DC Level Requirement for SerDes Reference Clocks.”

2.10.2

PCI Express DC Physical Layer Specifications

This section contains the DC specifications for the physical layer of PCI Express on this device.

Receiver

Transmitter

SD_TXn

SD_RXn

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