MPC8569E datasheet(58/127 Pages) FREESCALE

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MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Ethernet Interface

Freescale Semiconductor

The following figure provides the MII AC test load.

Figure 16. MII AC Test Load

The following figure shows the MII receive AC timing diagram.

Figure 17. MII Receive AC Timing Diagram

2.6.3.3

SMII AC Timing Specification

The following table shows the SMII timing specifications.

The following figure shows the SMII mode signal timing.

Figure 18. SMII Mode Signal Timing

Table 29. SMII Mode Signal Timing

For recommended operating conditions, see Table 3

Parameter

Symbol

Min

Max

Unit

Note

ETHSYNC_IN, ETHRXD to ETHCLOCK rising edge setup time

tSMDVKH

1.5

—

ETHCLOCK rising edge to ETHSYNC_IN, ETHRXD hold time

tSMDXKH

1.0

—

ETHCLOCK rising edge to ETHSYNC, ETHTXD output delay

tSMXR

1.5

5.5

—

Output

Z0 = 50 Ω

LVDD/2

RL = 50 Ω

RX_CLK

RXD[3:0]

tMRDXKL

tMRX

tMRXH

tMRXR

tMRXF

RX_DV

RX_ER

tMRDVKH

Valid Data

Valid

ETHCLOCK

ETHSYNC_IN

ETHRXD

ETHSYNC

ETHTXD

Valid

tSMXR

tSMDXKH

tSMDVKH

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