MPC8569E datasheet(1/127 Pages) FREESCALE

부품명	MPC8569E

상세설명	MPC8569E PowerQUICC III

PDF	127 Pages

Scroll/Zoom	100%

제조업체	FREESCALE [Freescale Semiconductor, Inc]

홈페이지	http://www.freescale.com

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1 / 127 page

FC–PBGA–783

29 mm

× 29 mm

Freescale Semiconductor

Data Sheet: Technical Data

Freescale reserves the right to change the detail specifications as may be required

to permit improvements in the design of its products.

• High-performance, 32-bit e500 core, scaling up to

1.33 GHz, that implements the Power Architecture®

technology

– 2799 MIPS at 1.33 GHz (estimated Dhrystone 2.1)

– 36-bit physical addressing

– Double-precision embedded floating point APU using

64-bit operands

– Embedded vector and scalar single-precision

floating-point APUs using 32- or 64-bit operands

– Memory management unit (MMU)

• Integrated L1/L2 cache

– L1 cache—32-Kbyte data and 32-Kbyte instruction

– L2 cache—512-Kbyte (8-way set associative)

• Two DDR2/DDR3 SDRAM memory controllers with full

ECC support

– One 64-bit or two 32-bit data bus configuration

– Up to 400 MHz clock (800 MHz data rate)

– Supporting up to 16 Gbytes of main memory

– Using ECC, detects and corrects all single-bit errors and

detects all double-bit errors and all errors within a nibble

– Invoke a level of system power management by

asserting MCKE SDRAM signal on-the-fly to put the

memory into a low-power sleep mode

– Both hardware and software options to support

battery-backed main memory

– Initialization bypass feature that allow system designers

to prevent re-initialization of main memory during

system power on following abnormal shutdown

• Integrated security engine (SEC) optimized to process all

the algorithms associated with IPsec, IKE, SSL/TLS,

iSCSI, SRTP, IEEE Std 802.11i™, IEEE Std 802.16™

(WiMAX), IEEE 802.1ae™ (MACSec), 3GPP, A5/3 for

GSM and EDGE, and GEA3 for GPRS.

– XOR engine for parity checking in RAID storage

applications

– Four crypto-channels, each supporting multi-command

descriptor chains

– Cryptographic execution units for PKEU, DEU, AESU,

AFEU, MDEU, KEU, CRCU, RNG and SEU- SNOW

• QUICC Engine technology

– Four 32-bit RISC cores

– Supports Ethernet, ATM, POS, and T1/E1 along with

associated interworking

– Four Gigabit Ethernet interfaces (up to two with

SGMII)

– Up to eight 10/100-Mbps Ethernet interfaces

– Up to 16 T1/E1 TDM links (512 × 64 channels)

– Multi-PHY UTOPIA/POS-PHY L2 interface

(16-bit)

– IEEE Std 1588™ v2 support

– SPI and Ethernet PHY management interface

– One full-/low-speed USB interface supporting USB 2.0

– General-purpose I/O signals

• High-speed interfaces (multiplexed) supporting:

– Two 1× Serial RapidIO interfaces (with message unit) or

one 4x interface

– ×4/×2/×1 PCI Express interface

– Two SGMII interfaces

• On-chip network switch fabric

• 133 MHz, 16-bit, 3.3 V I/O, enhanced local bus (eLBC)

with memory controller

• Enhanced secured digital host controller (eSDHC) used for

SD/MMC card interface

• Integrated four-channel DMA controller

• Dual I2C and dual universal asynchronous

receiver/transmitter (DUART) support

• Programmable interrupt controller (PIC)

• IEEE Std 1149.1™ JTAG test access port

• 1.0-V and 1.1-V core voltages with 3.3-V, 2.5-V, 1.8-V,

1.5-V and 1.0-V I/O

• 783-pin FC-PBGA package, 29 mm

× 29 mm

Document Number: MPC8569EEC

Rev. 1, 02/2012

MPC8569E PowerQUICC III

Integrated Processor

Hardware Specifications

MPC8569E

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