MPC8569E datasheet(71/127 Pages) FREESCALE

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Ethernet Interface

MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

2.6.4.2.4

SGMII Receiver AC Timing Specifications

The following table provides the SGMII receive AC timing specifications. The AC timing specifications do not include RefClk

jitter. Source synchronous clocking is not supported. Clock is recovered from the data.

The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in the unshaded region of the following

figure.

Figure 30. Single Frequency Sinusoidal Jitter Limits

Table 39. SGMII Receive AC Timing Specifications

At recommended operating conditions with XVDD = 1.0 V ± 3%. and 1.1 V ± 3%.

Parameter

Symbol

Min

Typ

Max

Unit

Notes

Deterministic Jitter Tolerance

0.37

—

UI p-p

1, 2, 4

Combined Deterministic and Random Jitter Tolerance

JDR

0.55

—

UI p-p

1, 2, 4

Total Jitter Tolerance

0.65

—

UI p-p

1, 2, 4

Bit Error Ratio

BER

—

10-12

——

Unit Interval

799.92

800.00

800.08

Notes:

1. Measured at receiver.

2. See RapidIO 1x/4x LP Serial Physical Layer Specification for interpretation of jitter specifications.

3. Each UI is 800 ps ± 100 ppm.

4. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is guar-

anteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.

8.5 UI p-p

0.10 UI p-p

22.1 kHz

1.875 MHz

20 MHz

Frequency

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