MPC8569E datasheet(69/127 Pages) FREESCALE

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Ethernet Interface

MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

2.6.4.1.3

SGMII DC Receiver Electrical Characteristics

The following table lists the SGMII DC receiver electrical characteristics. Source synchronous clocking is not supported. Clock

is recovered from the data.

2.6.4.2

SGMII AC Timing Specifications

This section discusses the AC timing specifications for the SGMII interface.

2.6.4.2.1

AC Requirements for SGMII SD_REF_CLK and SD_REF_CLK

Note that the SGMII clock requirements for SD_REF_CLK and SD_REF_CLK are intended to be used within the clocking

guidelines specified by Section 2.9.2.4, “AC Requirements for SerDes Reference Clocks.”

Table 37. SGMII DC Receiver Electrical Characteristics

At recommended operating conditions with XVDD = 1.0 V ± 3% and 1.1 V ± 3%.

Parameter

Symbol

Min

Typ

Max

Unit

Notes

DC Input voltage range

—

N/A

—

Input differential voltage

LSTS = 001

VRX_DIFFp-p

100

—

1200

2, 4

LSTS = 100

175

—

Loss of signal threshold

LSTS = 001

VLOS

—

100

3, 4

LSTS = 100

—

175

Receiver differential input impedance

ZRX_DIFF

—

120

—

Notes:

1. Input must be externally AC-coupled.

2. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage.

3. The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express. See

Section 2.10.2, “PCI Express DC Physical Layer Specifications,” and Section 2.10.3, “PCI Express AC Physical Layer

Specifications,” for further explanation.

4. The LSTS shown in this table refers to the LSTS2 or LSTS3 bit field of the MPC8569E‘s SerDes control register SRDSCR4.

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