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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MPC8569E 데이터시트(PDF) 77 Page - Freescale Semiconductor, Inc |
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MPC8569E 데이터시트(HTML) 77 Page - Freescale Semiconductor, Inc |
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77 / 127 page  HDLC, BISYNC, Transparent, and Synchronous UART Interfaces MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 77 The following table provides the input and output AC timing specifications for the synchronous UART protocols. The following figure provides the AC test load. Figure 35. AC Test Load Inputs—External clock input setup time tHEIVKH 4— ns — Inputs—Internal clock input hold time tHIIXKH 0— ns — Inputs—External clock input hold time tHEIXKH 1.3 — ns — Notes: 1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). 2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. Table 46. Synchronous UART AC Timing Specifications For recommended operating conditions, see Table 3 Characteristic Symbol1 Min Max Unit Notes Outputs—Internal clock delay tHIKHOV 011 ns 2 Outputs—External clock delay tHEKHOV 114 ns 2 Outputs—Internal clock high Impedance tHIKHOX 011 ns 2 Outputs—External clock high Impedance tHEKHOX 114 ns 2 Inputs—Internal clock input setup time tHIIVKH 10 — ns — Inputs—External clock input setup time tHEIVKH 8— ns — Inputs—Internal clock input hold time tHIIXKH 0— ns — Inputs—External clock input hold time tHEIXKH 1— ns — Notes: 1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). 2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. Table 45. HDLC, BISYNC, and Transparent AC Timing Specifications (continued) For recommended operating conditions, see Table 3 Characteristic Symbol1 Min Max Unit Notes Output Z0 = 50 Ω OVDD/2 RL = 50 Ω |
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