MPC8569E datasheet(61/127 Pages) FREESCALE

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Ethernet Interface

MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

2.6.3.5.1

TBI Transmit AC Timing Specifications

The following table provides the TBI transmit AC timing specifications.

The following figure shows the TBI transmit AC timing diagram.

Figure 22. TBI Transmit AC Timing Diagram

2.6.3.5.2

TBI Receive AC Timing Specifications

The following table provides the TBI receive AC timing specifications.

Table 32. TBI Transmit AC Timing Specifications

For recommended operating conditions, see Table 3

Parameter

Symbol

Min

Typ

Max

Unit

Note

GTX_CLK clock period

tGTX

—8.0

—

TCG[9:0] setup time GTX_CLK going high

tTTKHDV

2.0

—

GTX_CLK to TCG[9:0] delay time

tTTKHDX

1.0

—

GTX_CLK rise (20%–80%)

tTTXZ

0.7

—

GTX_CLK fall time (80%–20%)

tTTXF

0.7

—

Note:

1. Data valid tTTKHDV to GTX_CLK minimum setup time is a function of clock and maximum hold time

(min setup = cycle time – max delay).

Table 33. TBI Receive AC Timing Specifications

For recommended operating conditions, see Table 3

Parameter

Symbol

Min

Typ

Max

Unit

Note

PMA_RX_CLK[0:1] clock period

tTRX

—

16.0

—

PMA_RX_CLK[0:1] skew

tSKTRX

7.5

—

8.5

—

PMA_RX_CLK[0:1] duty cycle

tTRXH/tTRX

—

RCG[9:0] setup time to rising PMA_RX_CLK

tTRDVKH

2.5

—

GTX_CLK

TCG[9:0]

tTTX

tTTXH

tTTXR

tTTXF

tTTKHDV

tTTKHDX

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