 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
PM0056 데이터시트(PDF) 69 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
PM0056 데이터시트(HTML) 69 Page - STMicroelectronics |
|
|
69 / 156 page  DocID15491 Rev 5 69/156 PM0056 The Cortex-M3 instruction set Operation PUSH stores registers on the stack in order of decreasing register numbers, with the highest numbered register using the highest memory address and the lowest numbered register using the lowest memory address. POP loads registers from the stack in order of increasing register numbers, with the lowest numbered register using the lowest memory address and the highest numbered register using the highest memory address. See LDM and STM on page 67 for more information. Restrictions In these instructions: • ‘reglist’ must not contain SP • For the PUSH instruction, reglist must not contain PC • For the POP instruction, reglist must not contain PC if it contains LR When PC is in reglist in a POP instruction: • bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfword-aligned address. • If the instruction is conditional, it must be the last instruction in the IT block. Condition flags These instructions do not change the flags. Examples PUSH{R0,R4-R7} PUSH{R2,LR} POP{R0,R10,PC} |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
