PM0056 datasheet(22/156 Pages) STMICROELECTRONICS

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The Cortex-M3 processor

PM0056

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DocID15491 Rev 5

Handler mode always uses the MSP, so the processor ignores explicit writes to the active

stack pointer bit of the CONTROL register when in Handler mode. The exception entry and

return mechanisms update the CONTROL register.

In an OS environment, it is recommended that threads running in Thread mode use the

process stack and the kernel and exception handlers use the main stack.

By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode to

the PSP, use the MSR instruction to set the Active stack pointer bit to 1, see MSR on

page 101.

When changing the stack pointer, software must use an ISB instruction immediately after

the MSR instruction. This ensures that instructions after the ISB execute using the new

stack pointer. See ISB on page 100

2.1.4

Exceptions and interrupts

The Cortex-M3 processor supports interrupts and system exceptions. The processor and

the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An

exception changes the normal flow of software control. The processor uses handler mode to

handle all exceptions except for reset. See Exception entry on page 38 and Exception

return on page 39 for more information.

The NVIC registers control interrupt handling. See Memory protection unit (MPU) on

page 105 for more information.

2.1.5

Data types

The processor:

•

Supports the following data types:

–

32-bit words

–

16-bit halfwords

–8-bit bytes

•

supports 64-bit data transfer instructions.

•

manages all memory accesses (data memory, instruction memory and Private

Peripheral Bus (PPB)) as little-endian. See Memory regions, types and attributes on

page 25 for more information.

Bit 1

ASPSEL: Active stack pointer selection

Selects the current stack:

0: MSP is the current stack pointer

1: PSP is the current stack pointer.

In Handler mode this bit reads as zero and ignores writes.

Bit 0

TPL: Thread mode privilege level

Defines the Thread mode privilege level.

0: Privileged

1: Unprivileged.

Table 10. CONTROL register bit definitions (continued)

Bits

Function

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