PM0056 datasheet(40/156 Pages) STMICROELECTRONICS

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The Cortex-M3 processor

PM0056

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DocID15491 Rev 5

2.4

Fault handling

Faults are a subset of the exceptions, see Exception model on page 33. The following

generate a fault:

•

A bus error on:

–

An instruction fetch or vector table load

–

A data access

•

An internally-detected error such as an undefined instruction or an attempt to change

state with a BX instruction

•

Attempting to execute an instruction from a memory region marked as Non-Executable

(XN).

2.4.1

Fault types

Table 18 shows the types of fault, the handler used for the fault, the corresponding fault

status register, and the register bit that indicates that the fault has occurred. See

Configurable fault status register (SCB_CFSR) on page 142 for more information about the

fault status registers.

Table 17. Exception return behavior

EXC_RETURN[3:0]

Description

0bxxx0

Reserved.

0b0001

Return to Handler mode.

Exception return gets state from MSP.

Execution uses MSP after return.

0b0011

Reserved.

0b01x1

Reserved.

0b1001

Return to Thread mode.

Exception return gets state from MSP.

Execution uses MSP after return.

0b1101

Return to Thread mode.

Exception return gets state from PSP.

Execution uses PSP after return.

0b1x11

Reserved.

Table 18. Faults

Fault

Handler

Bit name

Fault status register

Bus error on a vector read

Hard fault

VECTTBL

Hard fault status register

(SCB_HFSR) on page 145

Fault escalated to a hard fault

FORCED

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