PM0056 datasheet(42/156 Pages) STMICROELECTRONICS

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The Cortex-M3 processor

PM0056

42/156

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2.4.3

Fault status registers and fault address registers

The fault status registers indicate the cause of a fault. For bus faults and memory

management faults, the fault address register indicates the address accessed by the

operation that caused the fault, as shown in Table 19.

2.4.4

Lockup

The processor enters a lockup state if a hard fault occurs when executing the NMI or hard

fault handlers. When the processor is in lockup state it does not execute any instructions.

The processor remains in lockup state until either:

•

It is reset

•

An NMI occurs

If lockup state occurs from the NMI handler a subsequent NMI does not cause the

processor to leave lockup state.

2.5

Power management

The STM32 and Cortex-M3 processor sleep modes reduce power consumption:

•

Sleep mode stops the processor clock. All other system and peripheral clocks may still

be running.

•

Deep sleep mode stops most of the STM32 system and peripheral clocks. At product

level, this corresponds to either the Stop or the Standby mode. For more details, please

refer to the “Power modes” Section in the STM32 reference manual.

The SLEEPDEEP bit of the SCR selects which sleep mode is used, see System control

modes see the STM32 product reference manual.

This section describes the mechanisms for entering sleep mode, and the conditions for

waking up from sleep mode.

Table 19. Fault status and fault address registers

Handler

Status register

name

Address register

name

Hard fault

HFSR

Hard fault status register (SCB_HFSR) on

page 145

Memory

management fault

MMFSR

MMFAR

Configurable fault status register (SCB_CFSR) on

page 142

Memory management fault address register

(SCB_MMFAR) on page 147

Bus fault

BFSR

BFAR

Configurable fault status register (SCB_CFSR) on

page 142

Bus fault address register (SCB_BFAR) on

page 147

Usage fault

UFSR

Configurable fault status register (SCB_CFSR) on

page 142

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