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PM0056 데이터시트(PDF) 85 Page - STMicroelectronics |
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PM0056 데이터시트(HTML) 85 Page - STMicroelectronics |
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85 / 156 page ![]() DocID15491 Rev 5 85/156 PM0056 The Cortex-M3 instruction set 3.6.2 UMULL, UMLAL, SMULL, and SMLAL Signed and unsigned long multiply, with optional accumulate, using 32-bit operands and producing a 64-bit result. Syntax op{cond} RdLo, RdHi, Rn, Rm where: • ‘op’ is one of: UMULL: Unsigned long multiply UMLAL: Unsigned long multiply, with accumulate SMULL: Signed long multiply SMLAL: Signed long multiply, with accumulate • ‘cond’ is an optional condition code (see Conditional execution on page 57) • ‘RdHi, RdLo’ are the destination registers. For UMLAL and SMLAL, they also hold the accumulating value. • ‘Rn, Rm’ are registers holding the operands Operation The UMULL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi. The UMLAL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers, adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo, and writes the result back to RdHi and RdLo. The SMULL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies these integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi. The SMLAL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies these integers, adds the 64-bit result to the 64-bit signed integer contained in RdHi and RdLo, and writes the result back to RdHi and RdLo. Restrictions In these instructions: • Do not use either SP or PC • RdHi and RdLo must be different registers Condition flags These instructions do not affect the condition code flags. Examples UMULLR0, R4, R5, R6; unsigned (R4,R0) = R5 x R6 SMLALR4, R5, R3, R8; signed (R5,R4) = (R5,R4) + R3 x R8 |
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