PM0056 datasheet(100/156 Pages) STMICROELECTRONICS

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The Cortex-M3 instruction set

PM0056

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DocID15491 Rev 5

3.9.4

DSB

Data Synchronization Barrier.

Syntax

DSB{cond}

where:

•

‘cond’ is an optional condition code, see Conditional execution on page 57.

Operation

DSB acts as a special data synchronization memory barrier. Instructions that come after the

DSB, in program order, do not execute until the DSB instruction completes. The DSB

instruction completes when all explicit memory accesses before it complete.

Condition flags

This instruction does not change the flags.

Examples

DSB ; Data Synchronisation Barrier

3.9.5

ISB

Instruction Synchronization Barrier.

Syntax

ISB{cond}

where:

•

‘cond’ is an optional condition code, see Conditional execution on page 57.

Operation

ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so

that all instructions following the ISB are fetched from cache or memory again, after the ISB

instruction has been completed.

Condition flags

This instruction does not change the flags.

Examples

ISB

; Instruction Synchronisation Barrier

3.9.6

MRS

Move the contents of a special register to a general-purpose register.

Syntax

MRS{cond} Rd, spec_reg

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