PM0056 datasheet(129/156 Pages) STMICROELECTRONICS

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PM0056

Core peripherals

4.4

System control block (SCB)

The System control block (SCB) provides system implementation information, and system

control. This includes configuration, control, and reporting of the system exceptions. The

CMSIS mapping of the Cortex-M3 SCB registers

To improve software efficiency, the CMSIS simplifies the SCB register presentation. In the

CMSIS, the byte array SHP[0] to SHP[12] corresponds to the registers SHPR1-SHPR3.

4.4.1

Auxiliary control register (SCB_ACTLR)

Address offset: 0x00 (base address = 0xE000 E008)

Reset value: 0x0000 0000

Required privilege: Privileged

The ACTLR register disables certain aspects of functionality within the processor. This

0x204

NVIC_IABR1

ACTIVE[63:32]

Reset Value

0000000 0000000000 00 00 0 0 0 0 0 0 0 0 0 0 0

0x208

NVIC_IABR2

Reserved

ACTIVE [80:64]

Reset Value

0 00 00 000 00 00 000 00

0x300

NVIC_IPR0

IP[3]

IP[2]

IP[1]

IP[0]

Reset Value

0000000 0000000000 00 00 0 0 0 0 0 0 0 0 0 0 0

0x320

NVIC_IPR20

Reserved

IP[80]

Reset Value

0000000 0000000000 00 00 0 0 0 0 0 0 0 0 0 0 0

SCB registers

Reserved

0xE00

NVIC_STIR

Reserved

INTID[8:0]

Reset Value

0 0 0 0 000 00

Table 44. NVIC register map and reset values (continued)

Offset

Reserved

DISF

OLD

DISD

EFW

BUF

DISM

CYCI

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