PM0056 datasheet(154/156 Pages) STMICROELECTRONICS

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Core peripherals

PM0056

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DocID15491 Rev 5

4.5.5

SysTick design hints and tips

The SysTick counter runs on the processor clock. If this clock signal is stopped for low

power mode, the SysTick counter stops.

Ensure software uses aligned word accesses to access the SysTick registers.

4.5.6

SysTick register map

The table provides shows the SysTick register map and reset values. The base address of

the SysTick register block is 0xE000 E010.

Bit 30

SKEW: SKEW flag

Reads as one. Calibration value for the 1 ms inexact timing is not known because TENMS is

not known. This can affect the suitability of SysTick as a software real time clock.

Bits 29:24

Reserved, must be kept cleared.

Bits 23:0

TENMS[23:0]: Calibration value

Indicates the calibration value when the SysTick counter runs on HCLK max/8 as external

clock. The value is product dependent, please refer to the Product Reference Manual, SysTick

Calibration Value section. When HCLK is programmed at the maximum frequency, the SysTick

period is 1ms.

If calibration information is not known, calculate the calibration value required from the

frequency of the processor clock or external clock.

Table 49. SysTick register map and reset values

Offset

0x00

STK_CTRL

Reserved

Reset Value

1 0 0

0x04

STK_LOAD

Reserved

RELOAD[23:0]

Reset Value

000000000 00 00 0 0 0 0 0 0 0 0 0 0 0

0x08

STK_VAL

Reserved

CURRENT[23:0]

Reset Value

000000000 00 00 0 0 0 0 0 0 0 0 0 0 0

0x0C

STK_CALIB

Reserved

TENMS[23:0]

Reset Value

000000000 00 00 0 0 0 0 0 0 0 0 0 0 0

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