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CS89712 데이터시트(PDF) 153 Page - Cirrus Logic

부품명 CS89712
상세설명  HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH 10BASE-T ETHERNET CONTROLLER
PDF  170 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS89712 데이터시트(HTML) 153 Page - Cirrus Logic

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CS89712
DS502PP2
153
Figure 25. Sequential Page Mode Read Cycles with Minimum Wait States
Notes:
1.tEXBST = 35 ns at 36.864 MHz
35 ns at 18.432 MHz
(Value for 36.864 MHz assumes 1 wait state.)
Maximum values for minimum wait states. This time can be extended by integer multiples of the
clock period (27 nsec at 36 MHz or 54 nsec at 18.432 MHz), by either driving EXPRDY low and/or
by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before
the data transfer. If low at this point, the transfer is delayed by one clock period where EXPRDY is
sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
2. Consecutive reads with sequential access enabled are identical except that the sequential access
wait state field is used to determine the number of wait states, and no idle cycles are inserted
between successive non-sequential ROM/expansion cycles. This improves performance so the
SQAEN bit should always be set where possible.
tEXBST
tEXBST
t3
tEXRD
t4
t3
t4
t3
t4
t5
t6
t1
Data in
Bus held
Data in
Data in
04
8
EXPCLK
nCS[5:0]
nMOE
A[27:4]
A[3:0]
WORD
D[31:0]
EXPRDY



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