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CS89712 데이터시트(PDF) 157 Page - Cirrus Logic |
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CS89712 데이터시트(HTML) 157 Page - Cirrus Logic |
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157 / 170 page ![]() CS89712 DS502PP2 157 T1 T2 T3 T4 CLK nRAS / nCAS / nWE NOP REF NOP T0 NOP NOP (ACT) CKE nCS all DQM DQ Bank sel A10 (prech sel) addr tRP tRC1 auto precharge Figure 30. SDRAM Refresh Cycles t15 t20 t16 t18 t19 t21 t17 t22 t23 CL[2] CL[1] FRM M DD[3:0] Figure 31. LCD Controller Timings Notes: 1. The figure shows the end of a line. 2. If FRM is high during the CL[1] pulse, this marks the first line in the display. 3. CL[2] low time is doubled during the CL[1] high pulse |
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