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CS89712 데이터시트(PDF) 154 Page - Cirrus Logic

부품명 CS89712
상세설명  HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH 10BASE-T ETHERNET CONTROLLER
PDF  170 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

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CS89712
154
DS502PP2
Figure 26. Consecutive Memory Write Cycles with Minimum Wait States
Notes: 1. tnCSWR = 35 nsec at 36.864 MHz, 70 ns at 18.432 MHz
Maximum values for minimum wait states. This time can be extended by integer multiples of the
clock period (27 nsec at 36 MHz or 54 nsec at 18.432 MHz), by either driving EXPRDY low and/or
by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK
before the data transfer. If low at this point, the transfer is delayed by one clock period where
EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown
for clarity.
2. Consecutive reads with sequential access enabled are identical except that the sequential access
wait state field is used to determine the number of wait states, and no idle cycles are inserted
between successive non-sequential ROM/expansion cycles. This improves performance so the
SQAEN bit should always be set where possible.
3. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as
this cannot be driven with valid timing under zero wait state conditions.
tnCSWR
tADWR
t5
t6
t2
t7
t2
Bus held
Write data
Write data
eXPCLK
nCS[5:0]
nMWE
A[27:0]
WORD
D[31:0]
nEXPRDY
t8



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