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CS89712 데이터시트(PDF) 159 Page - Cirrus Logic

부품명 CS89712
상세설명  HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH 10BASE-T ETHERNET CONTROLLER
PDF  170 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS89712 데이터시트(HTML) 159 Page - Cirrus Logic

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CS89712
DS502PP2
159
ETHERNET TIMING CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Unit
10BASE-T Receive
Allowable Received Jitter at Bit Cell Center
tTRX1
--
±13.5
ns
Allowable Received Jitter at Bit Cell Boundary
tTRX2
-
-
±13.5
ns
Carrier Sense Assertion Delay
tTRX3
-540
-
ns
Invalid Preamble Bits after Assertion of Carrier Sense
tTRX4
1-
2
bits
Carrier Sense Deassertion Delay
tTRX5
-270
-
ns
10BASE-T Link Integrity
First Transmitted Link Pulse after Last Transmitted Packet
tLN1
816
24
ms
Time Between Transmitted Link Pulses
tLN2
816
24
ms
Width of Transmitted Link Pulses
tLN3
60
100
200
ns
Minimum Received Link Pulse Separation
tLN4
2-
7
ms
Maximum Received Link Pulse Separation
tLN5
25
-
150
ms
Last Receive Activity to Link Fail (Link Loss Timer)
tLN6
50
-
150
ms
Ethernet EEPROM
EESK Setup time relative to EECS
tSKS
100
-
-
ns
EECS Setup time wrt
↑ EESK
tCCS
250
-
-
ns
EEDataOut Setup time wrt
↑ EESK
tDIS
250
-
-
ns
EEDataOut Hold time wrt
↑ EESK
tDIH
500
-
-
ns
EEDataIn Hold time wrt
↑ EESK
tDH
10
-
-
ns
EECS Hold time wrt
↓ EESK
tCSH
100
-
-
ns
Min EECS Low time during programming
tCS
1000
-
-
ns
tTRX3
RXD±
tTRX5
tTRX4
tTRX1
tTRX2
Carrier Sense (internal)
Figure 34. 10BASE-T Receive



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