PC87373 datasheet(161/174 Pages) NSC

161 / 174 page

13.0 Device Characteristics (Continued)

161

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13.4.3 Clock Timing

High-Frequency Clock Timing

Figure 51. High-Frequency Clock Waveform Timing

Figure 52. CLOCKI14 and Internal 48 MHz Domain Timing

Symbol Figure

Clock Input Parameters

Reference

Conditions

CLOCKI14

Units

Min

Typ

Max

tCH

Clock High Pulse Width1

1. Not tested. Guaranteed by design.

29.5

tCL

Clock Low Pulse Width1

29.5

tCP

Clock Period1 (50%-50%)

69.14

69.84

70.54

FCK

−

Clock Frequency

FCKTYP − 1%

14.31818

FCKTYP +1%

MHz

tCR

Clock Rise Time1 (20%-80%)

2. Recommended value

tCF

Clock Fall Time1 (80%-20%)

t14MW

Clock Wake-Up Time

VDD3 stable to clock

start toggling

System dependent

t14MVAL

Clock Valid Time1

Clock start toggling

to clock valid

System dependent

Sym. Fig.

Internal Clock Parameter

Reference

Conditions

INT48M

Units

Min

Typ

Max

tCP

51 Clock Period1 (50%-50%)

1. Not tested. Guaranteed by characterization.

20.83

FCK

− Clock Frequency

MHz

t48MD 52 Clock Wake-Up Time1

After Clock

Generator enabled

500

µs

tCL

tCP

tCH

VIH

VIL

VIH

tCF

tCR

CLOCKI14

(14.31818 MHz)

t14MW

48 MHz Domain

VDD3 (Power)

VDD3ONmin

tCP (CLOCKI14)

t14MVAL

CKVALID bit

(Internal)

Enable Clock Generator

(Internal)

t48MD

tCP (48 MHz)

(Internal)

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