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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PC87373 데이터시트(PDF) 164 Page - National Semiconductor (TI) |
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PC87373 데이터시트(HTML) 164 Page - National Semiconductor (TI) |
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164 / 174 page  13.0 Device Characteristics (Continued) 164 www.national.com Revision 1.1 LPC Signals Symbol Figure Description Reference Conditions Min Max Unit tVAL Outputs Output Valid Delay After RE of CLK 11 ns tON Outputs Float to Active Delay After RE of CLK 2 ns tOFF Outputs Active to Float Delay After RE of CLK 28 ns tSU Inputs Input Setup Time Before RE of CLK 7 ns tHL Inputs Input Hold Time After RE of CLK 0 ns tPDR Reset Outputs Rise Propagation Delay From RE of PCI_RESET to RE of PCIRST_OUT, PCIRST_OUT2 30 ns tR Reset Outputs Rise Time PCIRST_OUT, PCIRST_OUT2 50 ns tPDF Reset Outputs Fall Propagation Delay From FE of PCI_RESET to FE of IDE_RSTDRV 20 ns tF Reset Outputs Fall Time IDE_RSTDRV15 ns Leakage Only Leakage Only 0.285 VDD 0.615 VDD 0.4 VDD 0.4 VDD PCI_CLK LAD3 −LAD0, LDRQ, SERIRQ Outputs tVAL tON tOFF VDD3 = 3.3V ±10% tVAL LAD3 −LAD0, SERIRQ Output Enabled 0.4 VDD 0.4 VDD PCI_CLK LAD3 −LAD0, LFRAME PCI_RESET, SERIRQ Inputs VDD3 = 3.3V ±10% tHL tSU LPCPD |
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