PC87373 datasheet(163/174 Pages) NSC

163 / 174 page

13.0 Device Characteristics (Continued)

163

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Revision 1.1

13.4.4 LPC Interface Timing

The AC characteristics of the LPC interface meet the PCI Local Bus Specification (Rev 2.2 December 18, 1998) for 3.3V DC

signaling.

PCI_CLK and PCI_RESET

Symbol

Parameter

Min

Max

Units

tCYC

1. The PCI may have any clock frequency between nominal DC and 33 MHz. Device operational

parameters at frequencies under 16 MHz are guaranteed by design rather than by testing. The

clock frequency may be changed at any time during the operation of the system as long as the

clock edges remain “clean” (monotonic) and the minimum cycle high and low times are not vio-

lated. The clock may only be stopped in a low state.

PCI_CLK Cycle Time

tHIGH

PCI_CLK High Time2

2. Not tested. Guaranteed by characterization.

tLOW

PCI_CLK Low Time2

−

PCI_CLK Slew Rate2,3

3. Rise and fall times are speciﬁed in terms of the edge rate measured in V/ns. This slew rate must

be met across the minimum peak-to-peak portion of the clock wavering (0.2 * VDD3 to 0.6 *

VDD3) as shown below.

V/ns

−

PCI_RESET Slew Rate2,4

4. The minimum PCI_RESET slew rate applies only to the rising (de-assertion) edge of the reset

signal and ensures that system noise cannot make an otherwise monotonic signal appear to

bounce in the switching range.

mV/ns

tHIGH

tLOW

tCYC

0.6 VDD

0.2 VDD

0.5 VDD

0.4 VDD

0.3 VDD

0.4 VDD3 p-to-p

(minimum)

VDD3 = 3.3V ±10%

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