TNETV2501INPGF datasheet(22/197 Pages) TI1

22 / 197 page

Introduction

December 2002 − Revised November 2008

SPRS206K

Table 2−4. Signal Descriptions (Continued)

Name

Function

Other‡

Type†

Multiplexed

Signal Name

Parallel Port − Data Bus

D[31:16]

I/O/Z

C, D, E,

F, G, H,

The D[31:16] pins of the Parallel Port serve one of two functions: parallel general-purpose

input/output (PGPIO) signals PGPIO[19:4] or external memory interface (EMIF) data bus

signals EMIF.D[31:16]. The function of the D[31:16] pins is determined by the state of the

GPIO6 pin during reset. The D[31:16] pins are set to PGPIO[19:4] if GPIO6 is low during

reset. The D[31:16] pins are set to EMIF.D[31:16] if GPIO6 is high during reset. The

function of the D[31:16] pins will be set once the device is taken out of reset (RESET pin

transitions from a low to high state).

The D[31:16] bus includes bus holders to reduce the static power dissipation caused by

floating, unused pins. The bus holders also eliminate the need for external bias resistors

on unused pins. When the bus goes into a high-impedance state, the bus holders keep the

data bus at the logic level that was most recently driven. The bus holders are enabled at

reset and can be enabled/disabled through the External Bus Control Register (XBCR).

PGPIO[19:4]

I/O/Z

Parallel general-purpose I/O. PGPIO[19:4] is selected when GPIO6 is low during reset.

The PGPIO[19:4] signals are configured as inputs after reset.

EMIF.D[31:16]

I/O/Z

EMIF data bus. EMIF.D[31:16] is selected when GPIO6 is high during reset. The

EMIF.D[31:16] signals are set as inputs after reset.

D[15:0]

I/O/Z

C, D, E,

F, M

The D[15:0] pins of the Parallel Port serve one of two functions: external memory interface

(EMIF) data bus signals EMIF.D[15:0] or reserved pins. The function of the D[15:0] pins is

determined by the state of the GPIO6 pin during reset. The D[15:0] pins are reserved if

GPIO6 is low during reset. The D[15:0] pins are set to EMIF.D[15:0] if GPIO6 is high during

reset. The function of the D[15:0] pins will be set once the device is taken out of reset

(RESET pin transitions from a low to high state).

The D[15:0] bus includes bus holders to reduce the static power dissipation caused by

floating, unused pins. The bus holders also eliminate the need for external bias resistors

on unused pins. When the bus goes into a high-impedance state, the bus holders keep the

data bus at the logic level that was most recently driven. The bus holders are enabled at

reset and can be enabled/disabled through the External Bus Control Register (XBCR).

Reserved

I/O/Z

Reserved pins. These pins are reserved when GPIO6 is low during reset.

EMIF.D[15:0]

I/O/Z

EMIF data bus. EMIF.D[15:0] is selected when GPIO6 is high during reset. The

EMIF.D[15:0] signals are configured as inputs after reset.

† I = Input, O = Output, S = Supply, Z = High impedance

‡ Other Pin Characteristics:

A − Internal pullup [always enabled]

B − Internal pulldown [always enabled]

C − Hysteresis input

D − Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E − Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2)

determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode.

If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode.

F − Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G − Pin can be configured as a general-purpose input.

H − PIn can be configured as a general-purpose output.

− Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K − Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

− Fail-safe pin

M − Pin is in high-impedance during reset (RESET pin is low)

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