TNETV2501INPGF datasheet(64/197 Pages) TI1

64 / 197 page

Functional Overview

December 2002 − Revised November 2008

SPRS206K

3.9.3 EMIF Input Clock Selection

The EMIF may be clocked from an external asynchronous clock source through the ECLKIN pin if a specific

EMIF frequency is needed. The source for the EMIF clock can be specified through the EMIFCLKS pin. If

EMIFCLKS is low, then the EMIF will be clocked via the same internal clock that feeds the data bridge module

and performance will be optimal. If EMIFCLKS is high, then an external asynchronous clock, which can be

taken up to 100 MHz, will clock the EMIF. The data throughput performance may be degraded due to

synchronization issues when an external clock source is used for the EMIF.

3.9.4 Changing the Clock Group Frequencies

DSP software can be used to change the clock frequency of each clock group by setting adequate values in

the PLL control registers. Figure 3−14 shows which PLL control registers affect the different portions of the

clock generator. The following sections describe the procedures for changing the frequencies of each clock

group.

Point A

Divider

Point B

PLL Core

Multiplier M1

Divider

OD1

PLLM

PLLDIV0

PLLDIV2

PLLDIV1

CK3SEL

WKEN

OSCDIV1

PLLDIV3

PLLCSR

PLLEN

Point C

Oscillator Power-Down Control

SYSCLK1

SYSCLK2

SYSCLK3

CLKOUT3

OSCOUT

X2/CLKIN

CLKMD0

Figure 3−14. Clock Generator Registers

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