TNETV2501INPGF datasheet(74/197 Pages) TI1

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Functional Overview

December 2002 − Revised November 2008

SPRS206K

3.9.5.9

CLKOUT3 Select Register (CK3SEL)

This register controls which clock is output onto the CLKOUT3 so that it may be used to test and debug

the PLL (in addition to its normal function of being a direct input clock divider). Modes other than

CK3SEL = 1011 are intended for debug use only and should not be used during normal operation.

Reserved

R, 00000000

Reserved

CK3SEL

R, 0000

R/W, 1011

LEGEND: R = Read, W = Write, n = value at reset

Figure 3−23. CLKOUT3 Select Register Layout (0x1C82)

Table 3−20. CLKOUT3 Select Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

Reserved

15:4

000000000000

Reserved. Reads return 0. Writes have no effect.

CK3SEL

3:0

R/W

1011

Output on CLK3SEL pin†

CK3SEL = 1001

CLKOUT3 becomes point A in Figure 3−14

CK3SEL = 1010

CLKOUT3 becomes point B in Figure 3−14

CK3SEL = 0000−0111

CLKOUT3 becomes oscillator divider output

in Figure 3−14

CK3SEL = 1011

CLKOUT3 becomes point C in Figure 3−14

CK3SEL = Other

Not supported

† The different options for the CLKOUT3 signal are intended for test purposes; it is recommended that the CK3SEL bits of the CK3SEL register

be kept at their default value of ‘1011b’ during normal operation.

3.9.5.10 CLKOUT Selection Register (CLKOUTSR)

As described in Section 3.9.2, Clock Groups, the 5501 has different clock groups, each of which can be driven

by a clock that is different from the CPU clock. The CLKOUT Selection Register determines which clock signal

is reflected on the CLKOUT pin.

Reserved

R, 00000000

Reserved

CLKOSEL

CLKOUTDIS

R, 00000

R/W, 01

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3−24. CLKOUT Selection Register Layout (0x8400)

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