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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TNETV2501INPGF 데이터시트(PDF) 97 Page - Texas Instruments |
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TNETV2501INPGF 데이터시트(HTML) 97 Page - Texas Instruments |
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97 / 197 page  Functional Overview 97 December 2002 − Revised November 2008 SPRS206K 3.11.2.3 Parallel GPIO Data Register 0 (PGPIODAT0) 15 14 13 12 11 10 9 8 IO15DAT IO14DAT IO13DAT IO12DAT IO11DAT IO10DAT IO9DAT IO8DAT R/W, pin R/W, pin R/W, pin R/W, pin R/W, pin R/W, pin R/W, pin R/W, pin 76 54 32 10 IO7DAT IO6DAT IO5DAT IO4DAT IO3DAT IO2DAT IO1DAT IO0DAT R/W, pin R/W, pin R/W, pin R/W, pin R/W, pin R/W, pin R/W, pin R/W, pin LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin. Figure 3−36. Parallel GPIO Data Register 0 Layout (0x4402) Table 3−38. Parallel GPIO Data Register 0 Bit Field Description† BIT NAME BIT NO. ACCESS RESET VALUE DESCRIPTION IOxDAT 15−0 R/W Depends on the signal level on the corresponding I/O pin Data bits that are used to either control the level of the corresponding I/O pins configured as output pins or to monitor the level of the corresponding I/O pins configured as input pins. The function of the data register bits is determined by the setting of the direction register bits. See Table 3−35, TMS320VC5501 PGPIO Cross-Reference to determine which device pins correspond to the PGPIO pins. If IOxEN = 0 and IOxDIR = 0, then IOxDAT is used to read the value of the PGPIOx pin: IOxDAT = 0: PGPIOx pin is read as a low IOxDAT = 1: PGPIOx pin is read as a high If IOxEN = 1 and IOxDIR = 1, then IOxDAT is used to set the value of the PGPIOx pin: IOxDAT = 0: Set PGPIOx pin to low IOxDAT = 1: Set PGPIOx pin to high Note that other combinations of IOxEN and IOxDIR are not supported—i.e., IOxEN and IOxDIR must always be set to the same value. † x = value from 0 to 15 |
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