TNETV2501INPGF datasheet(33/197 Pages) TI1

33 / 197 page

Introduction

December 2002 − Revised November 2008

SPRS206K

Table 2−4. Signal Descriptions (Continued)

Name

Function

Other‡

Type†

Multiplexed

Signal Name

General-Purpose I/O Pins

GPIO7

GPIO6

GPIO5

GPIO4

GPIO3

GPIO2/BOOTM2

GPIO1/BOOTM1

GPIO0/BOOTM0

I/O/Z

F, G, H,

General-purpose configurable inputs/outputs. GPIO[7:0] can be individually

configured as inputs or outputs via the GPIO Direction Register (IODIR). Data can be read

from inputs or written to outputs via the GPIO Data Register (IODATA). The GPIO pins are

configured as inputs after reset.

NOTE: the GPIO7 pin must be low during the rising edge of the reset signal for the device

to operate properly.

Boot mode selection signals. GPIO[2:0]/BOOTM[2:0] are sampled following reset to

configure the boot mode for the DSP. After the boot is completed, these pins can be used

as general-purpose inputs/outputs.

The GPIO4 pin is also used as an output for handshaking purposes on some of the boot

modes. Although this pin is not involved in boot mode selection, users should be aware

that this pin will become active as an output during the boot-load process and should

design accordingly. After the boot-load process is complete, the loaded application may

change the function of the GPIO4 pin.

Input clock source selection. The CLKMD0 bit of the Clock Mode Control Register

(CLKMD) determines which clock, either OSCOUT or X2/CLKIN, is used as an input clock

source to the DSP. If GPIO4 is low at reset, the CLKMD0 bit of the Clock Mode Control

generate an input clock (OSCOUT) for the DSP. If GPIO4 is high, the CLKMD0 bit will be

set to ‘1’ and the input clock will be taken directly from the X2/CLKIN pin.

An external crystal must be attached to the X1 and X2/CLKIN pins when the internal

oscillator is used to generate a clock to the DSP. Otherwise, when the oscillator is not

used to generate the input clock for the DSP, an externally generated 3.3-V clock must be

applied to the X2/CLKIN pin and the X1 pin must be left unconnected.

Function selection for multiplexed pins. The GPIO6 pin is used to select the function of

the multiplexed signals in the Parallel Port and the Host Port. The 5501 will be configured

in PGPIO mode (EMIF and HPI are disabled) when the GPIO6 pin is low during reset. The

5501 will be configured in EMIF/HPI mode when the GPIO6 pin is high during reset. The

function of the multiplexed signals will be set once the device is taken out of reset (RESET

pin transitions from a low to high state).

O/Z

External output (latched software-programmable signal). XF is set high by the BSET XF

instruction, set low by BCLR XF instruction, or by loading ST1. XF is used for signaling

other processors in multiprocessor configurations or used as a general-purpose output

pin. The XF pin is set to a value of ‘1’ during reset.

† I = Input, O = Output, S = Supply, Z = High impedance

‡ Other Pin Characteristics:

A − Internal pullup [always enabled]

B − Internal pulldown [always enabled]

C − Hysteresis input

D − Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E − Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2)

determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode.

If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode.

F − Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G − Pin can be configured as a general-purpose input.

H − PIn can be configured as a general-purpose output.

− Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K − Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

− Fail-safe pin

M − Pin is in high-impedance during reset (RESET pin is low)

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