TNETV2501INPGF datasheet(95/197 Pages) TI1

95 / 197 page

Functional Overview

December 2002 − Revised November 2008

SPRS206K

Table 3−35. TMS320VC5501 PGPIO Cross-Reference (Continued)

PARALLEL/HOST PORT MUX MODE = 1

(FULL EMIF)

PARALLEL/HOST PORT MUX MODE = 0

(PGPIO)

HPI Data Bus

HD[7:0]

PGPIO[43:36]

HPI.HD[7:0]

HPI Control Bus

HC0

PGPIO44

HPI.HAS

HC1

PGPIO45

HPI.HBIL

3.11.2.1

Parallel GPIO Enable Register 0 (PGPIOEN0)

IO15EN

IO14EN

IO13EN

IO12EN

IO11EN

IO10EN

IO9EN

IO8EN

R/W, 0

IO7EN

IO6EN

IO5EN

IO4EN

IO3EN

IO2EN

IO1EN

IO0EN

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3−34. Parallel GPIO Enable Register 0 Layout (0x4400)

Table 3−36. Parallel GPIO Enable Register 0 Bit Field Description†

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

IOxEN

15−0

R/W

0000000000000000

Enable or disable output function of the corresponding I/O pins.

See Table 3−35, TMS320VC5501 PGPIO Cross-Reference to deter-

mine which device pins correspond to the PGPIO pins.

IOxEN = 0:

Output function of the PGPIOx pin is disabled—i.e., the

pin cannot drive an output signal; it can only be used as

an input. When IOxEN = 0, IOxDIR must also be

cleared to 0.

IOxEN = 1:

Output function of the PGPIOx pin is enabled—i.e., the

pin is used to drive an output signal. When IOxEN = 0,

IOxDIR must also be set to 1; otherwise, the output

value is undefined.

† x = value from 0 to 15

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