TNETV2501INPGF datasheet(98/197 Pages) TI1

98 / 197 page

Functional Overview

December 2002 − Revised November 2008

SPRS206K

3.11.2.4

Parallel GPIO Enable Register 1 (PGPIOEN1)

IO31EN

IO30EN

IO29EN

IO28EN

IO27EN

IO26EN

IO25EN

IO24EN

R/W, 0

IO23EN

IO22EN

IO21EN

IO20EN

IO19EN

IO18EN

IO17EN

IO16EN

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3−37. Parallel GPIO Enable Register 1 Layout (0x4403)

Table 3−39. Parallel GPIO Enable Register 1 Bit Field Description†

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

IOxEN

15−0

R/W

0000000000000000

Enable or disable output function of the corresponding I/O pins.

See Table 3−35, TMS320VC5501 PGPIO Cross-Reference to deter-

mine which device pins correspond to the PGPIO pins.

IOxEN = 0:

Output function of the PGPIOx pin is disabled—i.e.,

the pin cannot drive an output signal; it can only be

used as an input. When IOxEN = 0, IOxDIR must

also be cleared to 0.

IOxEN = 1:

Output function of the PGPIOx pin is enabled—i.e.,

the pin is used to drive an output signal. When

IOxEN = 0, IOxDIR must also be set to 1;

otherwise, the output value is undefined.

† x = value from 16 to 31

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