TNETV2501INPGF datasheet(101/197 Pages) TI1

101 / 197 page

Functional Overview

101

December 2002 − Revised November 2008

SPRS206K

3.11.2.7

Parallel GPIO Enable Register 2 (PGPIOEN2)

Reserved

IO45EN

IO44EN

IO43EN

IO42EN

IO41EN

IO40EN

R/W, 00

R/W, 0

IO39EN

IO38EN

IO37EN

IO36EN

IO35EN

IO34EN

IO33EN

IO32EN

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3−40. Parallel GPIO Enable Register 2 Layout (0x4406)

Table 3−42. Parallel GPIO Enable Register 2 Bit Field Description†

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

Reserved

15−14

R/W

Reserved

IOxEN

13−0

R/W

00000000000000

Enable or disable output function of the corresponding I/O pins.

See Table 3−35, TMS320VC5501 PGPIO Cross-Reference to deter-

mine which device pins correspond to the PGPIO pins.

IOxEN = 0:

Output function of the PGPIOx pin is disabled—i.e.,

the pin cannot drive an output signal; it can only be

used as an input. When IOxEN = 0, IOxDIR must

also be cleared to 0.

IOxEN = 1:

Output function of the PGPIOx pin is enabled—i.e.,

the pin is used to drive an output signal. When

IOxEN = 0, IOxDIR must also be set to 1;

otherwise, the output value is undefined.

† x = value from 32 to 45

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